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FEATURES
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LT3688 Dual 800mA Step-Down Switching Regulator with Power-On Reset and Watchdog Timer DESCRIPTION
The LT(R)3688 is an adjustable frequency (350kHz to 2.2MHz) dual monolithic step-down switching regulator with two power-on reset timers and a watchdog timer. The regulator operates off inputs up to 36V. Low ripple Burst Mode(R) operation maintains high efficiency at low output current while keeping output ripple below 25mV in a typical application, with input quiescent current of just 115A. Shutdown circuitry reduces input supply current to less than 1A while EN/UVLO is pulled low. The reset and watchdog timeout periods are both adjustable using external capacitors. Tight accuracy specifications and glitch immunity ensure reliable reset operation without false triggering. The open collector RST pins will pull down if the monitored output voltage drops 10% below the programmed value. The LT3688 watchdog timer monitors for watchdog falling edges grouped too close together or too far apart. The LT3688 is available in 24-Pin TSSOP and 4mm x 4mm QFN packages, each with an exposed pad for low thermal resistance.
Wide Input Range: Operation from 3.8V to 36V Low Ripple (<25mVP-P) Burst Mode Operation: IQ = 115A at 12VIN to 3.3V and 5V Programmable, Defeatable Window Watchdog Timer Two Independently Programmable Power-On-Reset Timers Synchronizable, Adjustable 350kHz-2.2MHz Switching Frequency Two 800mA Output Switching Regulators with Internal Power Switches Programmable Input Undervoltage Lockout with Hysteresis Thermally Enhanced 24-Pin TSSOP and 4mm x 4mm QFN Packages
APPLICATIONS
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Automotive Electronic Control Units Industrial Power Supplies High-Reliability Processor Systems
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
5V and 3.3V Regulator with Power-On Reset and Watchdog Timers
VIN 6V TO 36V
Efficiency
90 VIN = 12V VOUT = 3.3V L = 4.7H f = 800kHz 10000.0 1000.0 POWER LOSS (mW) 100.0 10.0 1.0 0.1 0.01 0.001 0.01 0.1 LOAD CURRENT (A) 1
3688 TA01b
4.7F
EN/UVLO BST1
VIN
BIAS BST2 0.22F 12H SW2 VOUT2 3.3V 800mA 22pF 1nF 100k 22F
80 EFFICIENCY (%) 70 60 50 40
1nF 4.7nF 4.7nF 110k
3688 TA01a
VOUT1 5V 800mA 22pF 22F
18H 523k
0.22F SW1 LT3688 DA1 FB1 DA2 FB2 RUN/SS2 CWDT CPOR1 CPOR2 RT SYNC
316k
100k 1nF RUN/SS1 P
I/O I/O RESET
WDI WDO RST1 RST2 GND
30 0.0001
fSW = 500kHz
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LT3688 ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, EN/UVLO, CONFIG Voltage (Note 2)...................36V BST Voltage ..............................................................55V BST above SW Voltage .............................................30V BIAS Voltage .............................................................30V WDE, WDI, RST, WDO Voltage ...................................6V FB, RT , SYNC, RUN/SS Voltage ..................................6V CWDT , CPOR Voltage ....................................................3V
Operating Junction Temperature Range (Note 3) LT3688E, LT3688I ..............................-40C to 125C LT3688H ............................................-40C to 150C Maximum Junction Temperature LT3688E, LT3688I ............................................. 125C LT3688H ........................................................... 150C Storage Temperature Range...................-65C to 150C Lead Temperature (Soldering, 10 sec) FE Package ....................................................... 300C
PIN CONFIGURATION
TOP VIEW CWDT FB1 RUN/SS1 BST1 SW1 DA1 VIN CONFIG DA2 SW2 1 2 3 4 5 6 7 8 9 25 GND 24 EN/UVLO 23 SYNC 22 RT 21 CWDT 20 CPOR1 19 BIAS 18 CPOR2 17 WDI 16 WDE 15 WDO 14 RST1 13 RST2 RT 1 SYNC 2 EN/UVLO 3 FB1 4 RUN/SS1 5 BST1 6 7 SW1 8 DA1 9 10 11 12 CONFIG DA2 SW2 VIN 25 GND TOP VIEW CPOR1 CPOR2 BIAS WDE 18 WDO 17 RST1 16 RST2 15 FB2 14 RUN/SS2 13 BST2 WDI
24 23 22 21 20 19
BST2 10 RUN/SS2 11 FB2 12
FE PACKAGE 24-LEAD PLASTIC TSSOP JA = 38C/W EXPOSED PAD (PIN 25) IS GND, MUST BE ELECTRICALLY CONNECTED TO PCB
UF PACKAGE 24-LEAD (4mm x 4mm) PLASTIC QFN JA = 37C/W EXPOSED PAD (PIN 25) IS GND, MUST BE ELECTRICALLY CONNECTED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LT3688EFE#PBF LT3688IFE#PBF LT3688HFE#PBF LT3688EUF#PBF LT3688IUF#PBF TAPE AND REEL LT3688EFE#TRPBF LT3688IFE#TRPBF LT3688HFE#TRPBF LT3688EUF#TRPBF LT3688IUF#TRPBF PART MARKING* LT3688FE LT3688FE LT3688FE 3688 3688 PACKAGE DESCRIPTION 24-Lead Plastic TSSOP 24-Lead Plastic TSSOP 24-Lead Plastic TSSOP 24-Lead (4mm x 4mm) Plastic QFN 24-Lead (4mm x 4mm) Plastic QFN TEMPERATURE RANGE -40C to 125C -40C to 125C -40C to 150C -40C to 125C -40C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LT3688 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VIN Undervoltage Lockout Quiescent Current from VIN VEN/UVLO = 0.3V VBIAS = 5V, Not Switching VBIAS = 0V, Not Switching VEN/UVLO = 0.3V VBIAS = 5V, Not Switching VBIAS = 0V, Not Switching
The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VIN = 12V, unless otherwise noted. (Note 3)
CONDITIONS
l l
MIN 3
TYP 3.5 0.01 65 235 0.01 155 -5
MAX 3.8 1 105 310 1 200 -20 0.810 0.814 -50 2.35 540 180 2.2 -1 1.6 2 2.5 25 1.35 6 5.5 -4 1 1.3 92 25.8 22 1.6 0.4 0.3 30 1.3
UNITS V A A A A A A V V nA %/V MHz kHz ns A mV A A A V mA V A A A A V V % ms ms ms ms V V s V A ns
Quiescent Current from BIAS
l
FB Voltage FB Pin Bias Current FB Voltage Line Regulation Switching Frequency Minimum Off-Time (Note 4) Switch Current Limit (Note 5) Switch VCESAT Switch Leakage Current (Note 8) DA Current Limit Boost Schottky Reverse Leakage Minimum BST Voltage above SW BST Pin Current EN/UVLO Threshold Voltage EN/UVLO Input Current Threshold Current Hysteresis RUN/SS Pin Current RUN/SS Switching Threshold SYNC Threshold Voltage VUV tRST tWDU tWDL tWDTO Reset Threshold Reset Timeout Period Watchdog Window Upper Boundary Watchdog Window Lower Boundary Watchdog Timeout Period RST Output Voltage Low tUV UV Detect to RST Asserted WDI Input Threshold WDI Input Pull-Up Current WDI Input Pulse Width WDE Threshold Voltage WDE Input Pull-Down Current WDO Output Voltage Low VWDE = 1.2V ISINK = 2.5mA ISINK = 100A % of FB Voltage, VFB Falling CPOR = 4700pF CWDT = 1000pF CWDT = 1000pF CWDT = 1000pF ISINK = 2.5mA, VFB = 0.6V ISINK = 100A, VFB = 0.6V VFB Set to 0.680V VRUN/SS = 0V VEN/UVLO = 1.35V VEN/UVLO = 1.15V ISW = 0.8A VBIAS = 0V VFB = 0.800V 5V < VIN < 36V RT = 20k, VBST = 12V RT = 110k, VBST = 12V VBST = 12V DC = 15% ISW = 0.8A
l l l l l l
0.790 0.784
0.800 -3 0.002
1.85 460 1.2
2.1 500 115 1.7 280 -0.01
l
0.9
1.2 0.01 2.15 15
l
1.15 2.5 2.5 -1.4 0.15 0.4
1.25 0.3 4 3.7 -2.8 0.8 0.8 90 23.5 20 1.25 2.5 0.2 0.01
l l l l l l l l l l l l
88 21.2 18 0.8
4 0.4 300 0.4
10 0.95 -2 0.65 3.5 0.2 0.01
1 0.4 0.3
V A V V
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LT3688 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER RST Pull-Up Current (Note 6) WDO Pull-Up Current (Note 6) CONFIG Low Level Input Voltage CONFIG High Level Input Voltage CONFIG Pin Voltage When Open Maximum CONFIG Input Current in Open State CONFIG Pin Bias Current VCONFIG = 0V, VIN Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Absolute Maximum Voltage at the VIN, CONFIG and EN/UVLO pins is 36V for continuous operation. Note 3: The LT3688 is tested under pulsed load conditions such that TJ = TA. The LT3688E is guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3688I is guaranteed over the full -40C to 125C operating junction temperature range. The LT3688H is guaranteed over the full -40C to 150C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125C. The junction temperature (TJ, in C) is calculated from the ambient temperature (TA, in C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD JA), where JA (in C/W) is the package thermal impedance.
l l l l
The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25C. VIN = 12V, unless otherwise noted. (Note 3)
CONDITIONS MIN -1.5 -1.5 1.4 0.64 1 20 TYP -2.5 -2.5 0.2 MAX UNITS A A V V V A A
Note 4: The LT3688 contains circuitry that extends the maximum duty cycle if the BST voltage is 2V greater than the SW voltage. See the Applications Information section for more details. Note 5: Current limit is guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycles. Note 6: The outputs of RST and WDO have a weak pull-up to VBIAS of typically 2.5A. However, external pull-up resistors may be used when faster rise times are required or for VOH higher than VBIAS. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when over-temperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 8: All currents into pins are positive; all voltages are referenced to GND unless otherwise specified.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency, VOUT = 5V
95 90 EFFICIENCY (%) EFFICIENCY (%) 85 80 75 70 65 0 0.2 0.4 0.6 LOAD CURRENT (A) 0.8 1
3688 G01
TA = 25C unless otherwise noted. Efficiency, VOUT = 1.8V
85 80 EFFICIENCY (%) 75 70 65 60 55 fSW = 500kHz VIN = 12V
Efficiency, VOUT = 3.3V
90 85 80 75 70 65 60 0 0.2 0.4 0.6 LOAD CURRENT (A) 0.8 1
3688 G02
fSW = 1MHz VIN = 12V
fSW = 1MHz VIN = 12V
0
0.2
0.4 0.6 LOAD CURRENT (A)
0.8
1
3688 G03
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LT3688 TYPICAL PERFORMANCE CHARACTERISTICS
No-Load Supply Current (Input)
160 140 SUPPLY CURRENT (A) 120 100 80 60 40 20 0 0 10 20 VIN (V) 30 40
3688 G04
TA = 25C unless otherwise noted. Maximum Load Current (5V)
2 fSW = 1MHz
No-Load Supply Current (Temperature)
3000 CATCH DIODE: B140HB VIN = 12V 2500 VOUT1 = 5V VOUT2 = 3.3V 2000 1500 1000 500 0 -50 -25 0 LOAD CURRENT (A)
VOUT1 = 5V VOUT2 = 3.3V SUPPLY CURRENT (A)
1.5
L = 15H L = 10H
INCREASED SUPPLY CURRENT DUE TO CATCH DIODE LEAKAGE AT HIGH TEMPERATURE
1
0.5
0
25 50 75 100 125 150 TEMPERATURE (C)
3688 G05
0
10
20 30 INPUT VOLTAGE (V)
40
3688 G06
Maximum Load Current (3.3V)
2 fSW = 1MHz L = 15H CURRENT LIMIT (A) L = 10H 1 1.8 1.6 1.5 LOAD CURRENT (A) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 10 20 30 INPUT VOLTAGE (V) 40
3688 G07
Switch Current Limit vs Duty Cycle
2.0 TYPICAL 1.5 MIN CURRENT LIMIT (A)
Switch Current Limit vs Temperature
1.0
0.5
0.5
0 0 20 40 60 DUTY CYCLE (%) 80 100
3688 G08
DC = 15% 0 -50 -25 0
25 50 75 100 125 150 TEMPERATURE (C)
3688 G09
Switch Voltage Drop
350 300 20 BST PIN CURRENT (mA) 250 200 150 100 50 0 0 200 400 600 800 SWITCH CURRENT (mA) 1000
3688 G10
BST Pin Current
25 0.810
Feedback Voltage
15
FEEDBACK VOLTAGE (V)
SWITCH VOLTAGE (mV)
0.805
0.800
10
5
0.795
0 0 200 400 600 800 SWITCH CURRENT (mA) 1000
3688 G11
0.790 -50 -20
0
25 50 75 100 125 150 TEMPERATURE (C)
3688 G12
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LT3688 TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency vs RT
2.5 SWITCHING FREQUENCY (MHz) SWITCHING FREQUENCY (MHz) 1.2 RT = 49.9k 2.0 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 -50 -20 MINIMUM ON TIME (ns) 150
TA = 25C unless otherwise noted. Minimum Switch On-Time
200 ISW = 700mA
Switching Frequency vs Temperature
1.5
100
1.0
0.5
50
0 0 50 100 RT (k) 150 200
3688 G13
0
25 50 75 100 125 150 TEMPERATURE (C)
3688 G14
0
25 50 75 100 125 150 TEMPERATURE (C)
3688 G16
EN/UVLO Pin Current
25 1.50
EN/UVLO Pin Threshold
900 THRESHOLD FALLING 800 EN/UVLO PIN THRESHOLD (V) FORWARD VOLTAGE (mV)
Boost Diode Forward Voltage
20 PIN CURRENT (A)
1.40
700 600 500 400 300 200 100
15
1.30
10
1.20
5
1.10
0 0 5 10 15 20 25 30 PIN VOLTAGE (V) 35 40
1.00 -50 -25
0
25 50 75 100 125 150 TEMPERATURE (C)
3688 G18
0 0 10 20 30 CURRENT (mA) 40 50
3688 G19
3688 G17
Switching Waveforms, Burst Mode Operation
IL 0.2A/DIV IL 0.2A/DIV
Switching Waveforms, Transition from Burst Mode to Full Frequency
IL 0.2A/DIV
Switching Waveforms, Full Frequency Continuous Operation
VSW 5V/DIV
VSW 5V/DIV
VSW 5V/DIV
VOUT 10mV/DIV 5s/DIV VIN = 12V; FRONT PAGE APPLICATION ILOAD = 7mA
3688 G20
VOUT 10mV/DIV 5s/DIV VIN = 12V; FRONT PAGE APPLICATION ILOAD = 40mA
3688 G21
VOUT 10mV/DIV 5s/DIV VIN = 12V; FRONT PAGE APPLICATION ILOAD = 160mA
3688 G22
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LT3688 TYPICAL PERFORMANCE CHARACTERISTICS
Power-On Reset Threshold vs Temperature
0.730 700 600 0.725 RESET DELAY (s) 20 500 400 300 200 5 100 0.710 -50 -25 0 0.1 0 -50 -25 tWDU (ms) 15
TA = 25C unless otherwise noted. Watchdog Window Mode Period vs Temperature
25 CWDT = 1000pF
Typical Transient Duration vs Comparator Overdrive
VUV (V)
0.720
10
0.715
0
25 50 75 100 TEMPERATURE (C)
125 150
3688 G23
1 10 OVERDRIVE VOLTAGE (% of VUV)
100
3688 G24
0
25 50 75 100 125 150 TEMPERATURE (C)
3688 G26
Reset Timeout Period (tRST ) vs Temperature
30 25 20 t RST (ms) 0 25 50 75 100 125 150 TEMPERATURE (C)
3688 G27
Reset Timeout Period (tRST ) vs Capacitance
100000 10000 1000 100 10 1
CPOR = 4700pF
tRST (ms)
15 10 5 0 -50 -25
0.1 0.01 0.001
0.1
10 CPOR (nF)
1000
100000
3688 G28
Watchdog Window Lower Boundary (tWDL) vs Capacitance
100000 10000 1000 t WDL (ms) 100 10 1 0.1 0.01 0.001 1 t WDU (ms) 100000 10000 1000 100 10
Watchdog Window Upper Boundary (tWDU) vs Capacitance
0.1
10 CWDT (nF)
1000
100000
3688 G29
0.1 0.001
0.1
10 CWDT (nF)
1000
100000
3688 G30
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LT3688 PIN FUNCTIONS
(QFN/TSSOP)
RT (Pin 1/Pin 22): The RT pin is used to set the internal oscillator frequency. Tie a resistor from RT to GND to set the switching frequency. SYNC (Pin 2/Pin 23): Drive the SYNC pin with a logiclevel signal with positive and negative pulse widths of at least 150ns. Do not float this pin. Tie to GND if the SYNC feature is not used. EN/UVLO (Pin 3/Pin 24): The EN/UVLO pin is used to put the LT3688 in shutdown mode. Pull the pin below 0.3V to shut down the LT3688. The 1.25V threshold can function as an accurate undervoltage lockout (UVLO), preventing the regulator from operating until the input voltage has reached the programmed level. FB1, FB2 (Pins 4, 15/Pins 1, 12): The LT3688 regulates the feedback pins to 0.800V. Connect the feedback resistor divider taps to this pin. RUN/SS1, RUN/SS2 (Pins 5, 14/Pins 2, 11): Place a capacitor from RUN/SS to GND to program the soft start period. Use a 1000pF or larger capacitor at these pins. To ensure the SS capacitors are discharged, internal circuitry pulls the RUN/SS pins low and disables switching during startup before initiating the soft-start sequence. Once the RUN/SS pins fall below 0.2V, the pull down turns off, the SS capacitors start charging again, and switching is enabled. Do not drive these pins directly. Use an open drain or collector to pull them low, if necessary. BST1, BST2 (Pins 6, 13/Pins 3, 10): The BST pins are used to provide drive voltage, higher than the input voltage, to the internal NPN power switches. SW1, SW2 (Pins 7, 12/Pins 4, 9): The SW pins are the outputs of the internal power switches. Connect these pins to the inductors, catch diodes and boost capacitors. DA1, DA2 (Pins 8, 11/Pins 5, 8): Tie the DA pin to the anode of the external catch Schottky diode. If the DA pin current exceeds 1.2A, which could occur in an overload or short-circuit condition, switching is disabled until the DA pin current falls below 1.2A. VIN (Pin 9/Pin 6): The VIN pin supplies current to the LT3688's internal circuitry and to the internal power switches and must be locally bypassed.
CONFIG (Pin 10/Pin 7): The CONFIG pin programs the start-up sequence of the two voltage regulators and the behavior of the power-on reset and watchdog timers. To select one of three configuration options, tie the CONFIG pin to VIN , tie the CONFIG pin to GND or leave the CONFIG pin floating. With the CONFIG pin tied to VIN , each reset output depends on its respective FB pin. Channel 2 only starts when FB1 rises above 0.72V, and the watchdog timer only starts when both RST pins go high. With the CONFIG pin tied to GND, both RST pins pull low until both FB pins rise above 0.72V and the POR timer programmed by CPOR1 expires. Again, channel 2 only starts when FB1 rises above 0.72V, and the watchdog timer only starts when both RST pins go high. Tie CPOR2 to GND if the CONFIG pin is tied low. With the CONFIG pin floating, both channels start coincidentally, each reset output depends on its respective FB pin, and the watchdog timer starts when RST1 goes high. RST1, RST2 (Pins 17, 16/Pins 14, 13): The RST pins are active low, open-drain logic outputs with a weak pull-up to BIAS. After VFB rises above 0.72V, the reset remains asserted for the period set by the capacitor on the CPOR pin. Tie the RST pins to BIAS with a 100k resistor for a stronger pull-up. WDO (Pin 18/Pin 15): WDO will go low if the microprocessor fails to drive the WDI pin of the LT3688 with the appropriate signal. Tie the WDO pin to BIAS with a 100k resistor for a stronger pull-up. Keep capacitive loading on this pin below 1000pF. WDE (Pin 19/Pin 16): The watchdog timer enable pin disables the watchdog timer if the WDE voltage exceeds 1V. Float this pin or tie to ground for normal operation. WDI (Pin 20/Pin 17): The watchdog timer input pin receives the watchdog signal from the microprocessor. If two or more negative edges occur on WDI before the programmed fast timer period or no negative edge occurs within the slow timer period, the part will pulse WDO low with a pulse width of 1/8th of the slow timer period. Drive the WDI pin with a pulse width of at least 300ns. BIAS (Pin 22/Pin 19): The BIAS pin supplies current to the internal circuitry when BIAS is above 3V, helping reduce input quiescent current. The internal Schottky diodes are connected from BIAS to BST, providing the charging path for the boost capacitors.
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LT3688 PIN FUNCTIONS
(QFN/TSSOP)
CPOR1, CPOR2 (Pins 23, 21/Pins 20, 18): Place a capacitor between this pin and ground to set the power-on-reset timeout period. CWDT (Pin 24/Pin 21): Place a capacitor between this pin and ground to set the fast and slow watchdog timer periods.
Exposed Pad (Pin 25/Pin 25): Ground. Tie the exposed pad directly to the ground plane. The exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. The device must be soldered to the circuit board for proper operation.
BLOCK DIAGRAM
VIN C1 ON OFF RT OUT1
EN/UVLO
VIN
SYNC
RT
BIAS
BST1 OUT1 C3 L1 C2 DA1 RSEN1
SWITCH LATCH R Q S
INTERNAL 0.8V REF
SLOPE COMP SLAVE OSCILLATOR MASTER OSCILLATOR
SLOPE COMP SLAVE OSCILLATOR
SW1
Burst Mode OPERATION DETECT VC CLAMP
ERROR AMP
+
R1 FB1
+ -
+ -
80mV R2 RUN/SS1
2.5A CPOR1
3.4V
VIN
22A
ADJUSTABLE RESET PULSE GENERATOR CONFIGURATION LOGIC
ADJUSTABLE RESET PULSE GENERATOR
RST1
TRANSITION DETECT
WATCHDOG TIMER THREE-STATE DECODE 22A 2A
WDI
WDE
CWDT
WDO
CONFIG
GND
3688 BD01
+ -
+ -
SWITCH LATCH R Q S DISABLE Burst Mode OPERATION DETECT VC VC CLAMP RC CC FB2 DA2 RSEN2 SW2 BST2 C5 L2 C4 OUT2
-+
+-
+ - + -
+
RUN/SS2
2.5A CPOR2
22A
RST2
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LT3688 OPERATION
The LT3688 is a constant-frequency, current mode stepdown regulator with two reset timers and a watchdog timer that perform microprocessor supervisory functions. Operation can be best understood by referring to the Block Diagram. Keeping the EN/UVLO pin at ground completely shuts off the part drawing minimal current from the VIN source. To turn on the internal bandgap and the rest of the logic circuitry, raise the EN/UVLO pin above the accurate threshold of 1.25V. Also, VIN needs to be higher than 3.5V for the part to start switching. Switching Regulator Operation An oscillator, with frequency set by RT, enables an RS flip flop, turning on the internal power switch. An amplifier and comparator monitor the current flowing between the VIN and SW pins, turning the switch off when this current reaches a level determined by the voltage at VC . An error amplifier measures the output voltage through an external resistor divider tied to the FB pin and servos the VC voltage. If the error amplifier's output increases, more current is delivered to the output; if it decreases, less current is delivered. An active clamp on the VC voltage provides current limit. The VC voltage is also controlled by the internal soft-start circuit during start-up or after a fault condition takes place. An internal regulator provides power to the control circuitry. The internal regulator normally draws current from the VIN pin, but if the BIAS pin is connected to an external voltage higher than 3V, bias current will be drawn from the external source (typically the regulated output voltage). This improves efficiency. The BIAS pin also provides a current path to the internal boost diode that charges up the boost capacitor. The switch driver operates either from the VIN or from the BST pin. An external capacitor is used to generate a voltage at the BST pin that is higher than the VIN supply. This allows the driver to fully saturate the internal NPN power switch for efficient operation. To further optimize efficiency, the LT3688 automatically switches to Burst Mode operation in light load situations. Between bursts, all circuitry associated with controlling the output switch is shut down, reducing the input supply current to 115A in a typical application. A comparator monitors the current flowing through the catch diode via the DA pin. This comparator delays switching if the diode current goes higher than 1.2A (typical) during a fault condition such as a shorted output with high input voltage. Switching will only resume once the diode current has fallen below the 1.2A limit. This way the DA comparator regulates the valley current of the inductor to 1.2A during short circuit. This will ensure that the part will survive a short-circuit event. Power-On Reset and Watchdog Timer Operation The LT3688 has two power-on reset comparators that monitor the regulated output voltages. If VOUT is 10% below the regulation value, the RST pin is pulled low. Once the output voltage crosses over 90% of the regulation value, a reset timer is started and RST is released after the programmed reset delay time. The reset delay is programmable through the CPOR pin. The watchdog typically monitors a microprocessor's activity. The watchdog can be enabled or disabled by applying a logic signal to the WDE pin. The watchdog timer requires successive negative edges on the WDI pin to come within a programmed time window to keep WDO from going low. If the time between the two negative WDI edges is too short or too long, then the WDO pin will be pulled low. When the WDO pin goes low, it stays low for a time period equivalent to 1/8th of the watchdog window upper boundary. The WDO pin will go high again once the timer expires or if the RST pin goes low. The watchdog window upper and lower boundaries can be set through the CWDT pin.
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LT3688 TIMING DIAGRAMS
Power-On Reset Timing
VOUT VUV tUV RST tRST
Watchdog Timing
t < tWDL WDI tWDTO
WDO tWDTO tWDU
3686 TD01
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LT3688 TIMING DIAGRAMS
VOUT1 VUV tRST1 RST1 VUV tRST2 RST2 tWDU WDO
VOUT2
WDI STARTUP TIMING (VCONFIG = HIGH)
VOUT1
VUV
VOUT2 RST1
VUV tRST1
RST2 tWDU WDO
WDI STARTUP TIMING (VCONFIG = LOW) VUV tRST1 RST1 VUV tRST2 RST2 tWDU WDO
VOUT1
VOUT2
WDI STARTUP TIMING (VCONFIG = OPEN)
tRST1 = PROGRAMMED RESET PERIOD (CPOR1) tRST2 = PROGRAMMED RESET PERIOD (CPOR2) tWDU = WATCHDOG WINDOW UPPER BOUNDRY VUV = RESET THRESHOLD
3688 TD
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LT3688 APPLICATIONS INFORMATION
Setting the Output Voltage The output voltage is programmed with a resistor divider between the output and the FB pin. Choose the 1% resistors according to: V R1= R2 OUT - 1 0.8V For reference designators, refer to the Block Diagram. Setting the Switching Frequency The LT3688 uses a constant-frequency PWM architecture that can be programmed to switch from 350 kHz to 2.2 MHz by using a resistor tied from the RT pin to ground. Table 1 shows the RT values for various switching frequencies
Table 1. Switching Frequency vs RT SWITCHING FREQUENCY (MHz)
0.35 0.5 0.6 0.7 0.8 0.9 1 1.2 1.4 1.6 1.8 2.1 2.3
RT (k)
165 110 88.7 75 64.9 56.2 49.9 40.2 33.2 27.4 23.2 20 17.4
where VIN is the typical input voltage, VOUT is the output voltage, VF is the catch diode drop (~0.5V) and VSW is the internal switch drop (~0.3V at maximum load). If the LT3688 is programmed to operate at a frequency higher than fSW(MAX) for a given input voltage, the LT3688 enters pulse skip mode, where it skips switching cycles to maintain regulation. At frequencies higher than fSW(MAX), the LT3688 no longer operates with constant frequency. The LT3688 enters pulse skip mode at frequencies higher than fSW(MAX) because of the limitation on the LT3688's minimum on time of 140ns (180ns for TJ > 125C). As the switching frequency is increased above fSW(MAX), the part is required to switch for shorter periods to maintain the same duty cycle. Delays associated with turning off the power switch dictate the minimum on-time of the part. When the required on-time decreases below the minimum on-time of 140ns, the switch pulse width remains fixed at 140ns (instead of becoming narrower) to accommodate the same duty cycle requirement. The inductor current ramps up to a value exceeding the load current and the output ripple increases. The part then remains off until the output voltage dips below the programmed value before it begins switching again. Maximum Operating Voltage Range The maximum input voltage for LT3688 applications depends on switching frequency, the absolute maximum ratings of the VIN and BST pins, and by the minimum duty cycle (DCMIN). The LT3688 can operate from input voltages up to 36V. DCMIN = tON(MIN) * fSW where tON(MIN) is equal to 140ns and fSW is the switching frequency. Running at a lower switching frequency allows a lower minimum duty cycle. The maximum input voltage before pulse-skipping occurs depends on the output voltage and the minimum duty cycle: V + VF VIN(PS) = OUT - VF + VSW DCMIN Example: f = 2.1MHz, VOUT = 3.3V DCMIN = 140ns * 2.1MHz = 0.294 3.3V + 0.5V VIN(PS) = - 0.5V + 0.3V = 12.7V 0.294
3688f
Operating Frequency Tradeoffs Selection of the operating frequency is a tradeoff between efficiency, component size and maximum input voltage. The advantage of high frequency operation is that smaller inductor and capacitor values may be used. The disadvantages are lower efficiency, and narrower input voltage range at constant-frequency. The highest constantswitching frequency (fSW(MAX)) for a given application can be calculated as follows: VOUT + VF fSW(MAX) = tON(MIN) ( VIN + VF - VSW )
13
LT3688 APPLICATIONS INFORMATION
The LT3688 will regulate the output voltage at input voltages greater than VIN(PS). For example, an application with an output voltage of 3.3V and switching frequency of 2.1MHz has a VIN(PS) of 12.7V, as shown in Figure 1. Figure 2 shows operation at 27V. Output ripple and peak inductor current have significantly increased. A saturating inductor may further reduce performance. In pulse skip mode, the LT3688 skips switching pulses to maintain output regulation. The LT3688 will also skip pulses at very low load currents. VIN(PS) vs load current is plotted in the Typical Performance section.
VOUT 50mV/DIV (AC) IL 500mA/DIV
Unlike many fixed frequency regulators, the LT3688 can extend its duty cycle by remaining on for multiple cycles. The LT3688 will not switch off at the end of each clock cycle if there is sufficient voltage across the boost capacitor (C3 in the Block Diagram). Eventually, the voltage on the boost capacitor falls and requires refreshing. Circuitry detects this condition and forces the switch to turn off, allowing the inductor current to charge up the boost capacitor. This places a limitation on the maximum duty cycle as follows: DCMAX = 90% This leads to a minimum input voltage of: V + VF VIN(MIN) = OUT - VF + VSW DCMAX where VF is the forward voltage drop of the catch diode (~0.4V) and VSW is the voltage drop of the internal switch (~0.3V at maximum load). Example: ISW=0.8A and VOUT = 3.3V 3.3V + 0.4V - 0.4 + 0.3V = 4V 90% For best performance in dropout, use a 1F or larger boost capacitor. VIN(MIN) = Inductor Selection and Maximum Output Current
2s/DIV
3688 F01
Figure 1. Operation Below Pulse-Skipping Voltage. VOUT = 3.3V and fSW = 2.1MHz
VOUT 50mV/DIV (AC) IL 500mA/DIV
2s/DIV
3688 F02
A good first choice for the inductor value is L = ( VOUT + VF ) * 1.8MHz fSW
Figure 2. Operation Above VIN(ps). VIN = 27V, VOUT = 3.3V and fSW = 2.1MHz. Output Ripple and Peak Inductor Current Increase
Minimum Operating Voltage Range The minimum input voltage is determined either by the LT3688's minimum operating voltage of ~3.6V or by its maximum duty cycle. The duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: DC = VOUT + VF VIN - VSW + VF
where VF is the voltage drop of the catch diode (~0.4V), fSW is in MHz, and L is in H. The inductor's RMS current rating must be greater than the maximum load current and its saturation current should be at least 30% higher. For robust operation in fault conditions (start-up or shortcircuit) and high input voltage (>30V), use an 8.2H or greater inductor with a saturation rating of 2.2A, or higher. For highest efficiency, the series resistance (DCR) should be less than 0.1. Table 2 lists several vendors and types that are suitable.
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LT3688 APPLICATIONS INFORMATION
Table 2. Inductor Vendors VENDOR
Murata TDK Toko
PART SERIES
LQH55D SLF7045 SLF10145 DC62CB D63CB D75C D75F CR54 CDRH74 CDRH6D38 CR75
TYPE
Open Shielded Shielded Shielded Shielded Shielded Open Open Shielded Shielded Open
URL
www.murata.com www.component.tdk.com www.toko.com
When the switch is off, the potential across the inductor is the output voltage plus the catch diode drop. This gives the peak-to-peak ripple current in the inductor IL =
(1- DC) ( VOUT + VF )
L*f
Sumida
www.sumida.com
where f is the switching frequency of the LT3688 and L is the value of the inductor. The peak inductor and switch current is I ISW(PK) = IL(PK) = IOUT + L 2 To maintain output regulation, this peak current must be less than the LT3688's switch current limit ILIM . ILIM is at least 1.25A for at low duty cycles and decreases linearly to 0.9A at DC = 0.9. The maximum output current is a function of the chosen inductor value: IOUT(MAX) = ILIM - IL 2 IL 2
The optimum inductor for a given application may differ from the one indicated by this simple design guide. A larger value inductor provides a higher maximum load current, and reduces the output voltage ripple. If your load is lower than the maximum load current, then you can relax the value of the inductor and operate with higher ripple current. This allows you to use a physically smaller inductor, or one with a lower DCR resulting in higher efficiency. Be aware that if the inductance differs from the simple rule above, then the maximum load current will depend on input voltage. In addition, low inductance may result in discontinuous mode operation, which further reduces maximum load current. Discontinuous operation occurs when IOUT is less than IL / 2. For details of maximum output current and discontinuous mode operation, see Linear Technology's Application Note AN44. Finally, for duty cycles greater than 50% (VOUT/VIN > 0.5), a minimum inductance is required to avoid sub-harmonic oscillations: 1.2MHz LMIN = ( VOUT + VF ) * fSW where VF is the voltage drop of the catch diode (~0.4V), fSW is in MHz, and LMIN is in H. The current in the inductor is a triangle wave with an average value equal to the load current. The peak switch current is equal to the output current plus half the peak-to-peak inductor ripple current. The LT3688 limits its switch current in order to protect itself and the system from overload faults. Therefore, the maximum output current that the LT3688 will deliver depends on the switch current limit, the inductor value, and the input and output voltages.
= 1.25A * (1- 0.3DC) -
Choosing an inductor value so that the ripple current is small will allow a maximum output current near the switch current limit. One approach to choosing the inductor is to start with the simple rule given above, look at the available inductors, and choose one to meet cost or space goals. Then use these equations to check that the LT3688 will be able to deliver the required output current. Note again that these equations assume that the inductor current is continuous. Input Capacitor Bypass the input of the LT3688 circuit with a ceramic capacitor of an X7R or X5R type. Y5V types have poor performance over temperature and applied voltage, and should not be used. A 2.2F to 4.7F ceramic capacitor is adequate to bypass the LT3688 and will easily handle the ripple current. Note that larger input capacitance is required when a lower switching frequency is used. If the input power source has high impedance, or there is significant inductance due to long wires or cables,
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LT3688 APPLICATIONS INFORMATION
additional bulk capacitance may be necessary. This can be provided with a lower performance electrolytic capacitor. Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input capacitor is required to reduce the resulting voltage ripple at the LT3688 input and to force this very high frequency switching current into a tight local loop, minimizing EMI. A 2.2F capacitor is capable of this task, but only if it is placed close to the LT3688 and the catch diode (see the PCB Layout section). A second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the LT3688. A ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank circuit. If the LT3688 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT3688's voltage rating. See Linear Technology's Application Note 88 for details. Output Capacitor and Output Ripple The output capacitor has two essential functions. Along with the inductor, it filters the square wave generated by the LT3688 to produce the DC output. In this role it determines the output ripple, and low impedance at the switching frequency is important. The second function is to store energy in order to satisfy transient loads and stabilize the LT3688's control loop. Ceramic capacitors have very low equivalent series resistance (ESR) and provide the best ripple performance. A good starting value is: COUT = 50 VOUT * fSW
Taiyo Yuden
High performance electrolytic capacitors can be used for the output capacitor. Low ESR is important, so choose one that is intended for use in switching regulators. The ESR should be specified by the supplier and should be 0.1 or less. Such a capacitor will be larger than a ceramic capacitor and will have a larger capacitance because the capacitor must be large to achieve low ESR. Table 3 lists several capacitor vendors.
Table 3. Capacitor Vendors VENDOR
Panasonic
PART SERIES
Ceramic Polymer Tantalum Ceramic Tantalum Ceramic Polymer Tantalum Ceramic Ceramic Tantalum Ceramic
COMMENTS
EEEF Series
Kemet Sanyo
T494, T495 POSCAP
Murata AVX
TPS Series
Catch Diode The catch diode conducts current only during switch-off time. Average forward current in normal operation can be calculated from: ID(AVG) = IOUT ( VIN - VOUT ) VIN
where fSW is in MHz and COUT is the recommended output capacitance in F. Use X5R or X7R types, which will provide low output ripple and good transient response. Transient performance can be improved with a high value capacitor, but a phase lead capacitor across the feedback resistor R1 may be required to get the full benefit (see the Compensation section).
where IOUT is the output load current. The only reason to consider a diode with a larger current rating than necessary for nominal operation is for the worst-case condition of shorted output. The diode current will then increase to the typical peak switch current limit. Peak reverse voltage is equal to the regulator input voltage. Use a Schottky diode with a reverse voltage rating greater than the input voltage. Table 4 lists several Schottky diodes and their manufacturers.
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LT3688 APPLICATIONS INFORMATION
Table 4. Capacitor Vendors Part Number
On Semiconductor MBR0520L MBR0540 MBRM120E MBRM140 Diodes Inc. B0530W B120 B130 B140HB DFLS140 30 20 30 40 40 0.5 1 1 1 1.1 510 500 500 20 40 20 40 0.5 0.5 1 1 620 530 550
VR (V)
IAVE (A)
VF at 1A (mV)
Ceramic Capacitors Ceramic capacitors are small, robust and have very low ESR. However, ceramic capacitors can cause problems when used with the LT3688 due to their piezoelectric nature. When in Burst Mode operation, the LT3688's switching frequency depends on the load current, and at very light loads the LT3688 can excite the ceramic capacitor at audio frequencies, generating audible noise. Since the LT3688 operates at a lower current limit during Burst Mode operation, the noise is typically very quiet. If this is unacceptable, use a high performance tantalum or electrolytic capacitor at the output. Frequency Compensation The LT3688 uses current mode control to regulate the output, which simplifies loop compensation. In particular, the LT3688 does not require the ESR of the output capacitor for stability, allowing the use of ceramic capacitors to achieve low output ripple and small circuit size. Figure 3 shows an equivalent circuit for the LT3688 control loop. The error amp is a transconductance amplifier with finite output impedance. The power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance amplifier generating an output current proportional to the voltage at the VC node. Note that the output capacitor, C1, integrates this current, and that the capacitor on the VC node (CC) integrates the error amplifier output current, resulting in two poles in the loop. RC provides a zero.
With the recommended output capacitor, the loop crossover occurs above the RCCC zero. This simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. With a larger ceramic capacitor (very low ESR), crossover may be lower and a phase lead capacitor (CPL) across the feedback divider may improve the phase margin and transient response. At minimum, use a 10pF phase lead capacitor to reduce noise injection to the FB pin. If the output capacitor is different than the recommended capacitor, stability should be checked across all operating conditions, including load current, input voltage and temperature. The LT1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. Figure 4 shows the transient response when the load current is stepped from 300mA to 600mA and back to 300mA.
LT3688 0.7V CURRENT MODE POWER STAGE OUT FB R1 CPL
VC RC 80k CC 100pF GND
3M ERROR AMPLIFIER
Figure 3. Model for the Loop Response
VOUT 100mV/DIV
ILOAD 200mA/DIV
Figure 4. Transient Load Response of the LT3688 Front Page Application as the Load Current is Stepped from 300mA to 600mA
+
gm = 300A/V
-
- +
gm = 1.6A/V
800mV
ESR
+
C1 R2
C1
TANTALUM OR CERAMIC ELECTROLYTIC
3688 F03
50s/DIV
3688 F04
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LT3688 APPLICATIONS INFORMATION
Low Ripple Burst Mode Operation To enhance efficiency at light loads, the LT3688 operates in low ripple Burst Mode operation that keeps the output capacitor charged to the proper voltage while minimizing the input quiescent current. During Burst Mode operation, the LT3688 delivers single cycle bursts of current to the output capacitor followed by sleep periods where the output power is delivered to the load by the output capacitor. Because the LT3688 delivers power to the output with single, low current pulses, the output ripple is kept below 25mV for a typical application. In addition, VIN and BIAS quiescent currents are reduced to typically 65A and 155A, respectively, during the sleep time. As the load current decreases towards a no-load condition, the percentage of time that the LT3688 operates in sleep mode increases and the average input current is greatly reduced, resulting in high efficiency even at very low loads (see Figure 5). At higher output loads the LT3688 will be running at the frequency programmed by the RT resistor, and will be operating in standard PWM mode. The transition between PWM and low ripple Burst Mode operation is seamless, and will not disturb the output voltage. The front page application circuit will switch at full frequency at output loads higher than about 60mA. three ways to arrange the boost circuit. The BST pin must be more than 2.3V above the SW pin for best efficiency. For outputs of 3V and above, the standard circuit (Figure 6a) is best. For outputs between 2.8V and 3V, use a 1F boost capacitor. A 2.5V output presents a special case because it is marginally adequate to support the boosted drive stage while using the internal boost diode. For reliable BST pin operation with 2.5V outputs, use a good external Schottky diode (such as the ON semi MBR0540), and a 1F boost capacitor (see Figure 6b). For lower output voltages, the boost diode can be tied to the input (Figure 6c), or to another supply greater than 2.8V. The circuit in Figure 6a is more efficient because the BST pin current and BIAS pin quiescent current comes from a lower voltVOUT BIAS BST VIN VIN LT3688 SW 4.7F GND C3
(6a) For VOUT > 2.8V
VOUT BIAS BST D2
IL 0.2A/DIV VSW 5V/DIV VOUT 10mV/DIV
VIN
VIN LT3688 SW
C3
4.7F
GND
(6b) For 2.5V < VOUT < 2.8V
5s/DIV
3688 F05
VOUT
Figure 5. Burst Mode Operation
VIN
BIAS BST VIN LT3688 SW
BST and BIAS Pin Considerations Capacitor C3 and the internal boost Schottky diodes (see the Block Diagram) are used to generate boost voltages that are higher than the input voltage. In most cases, a 0.22F capacitor will work well. For the best performance in dropout, use a 1F or larger capacitor. Figure 6 shows
4.7F GND
C3
3688 F06
(6c) For VOUT < 2.5V; VIN(MAX) = 30V
Figure 6. Three Circuits for Generating the Boost Voltage
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LT3688 APPLICATIONS INFORMATION
age source. However, the full benefit of the BIAS pin is not realized unless it is at least 3V. Ensure that the maximum voltage ratings of the BST and BIAS pins are not exceeded. The minimum operating voltage of an LT3688 application is limited by the minimum input voltage (3.6V) and by the maximum duty cycle, as outlined in a previous section. For proper start-up, the minimum input voltage is also limited by the boost circuit. If the input voltage is ramped slowly, or the LT3688 is turned on with its EN/UVLO pin when the output is already in regulation, then the boost capacitor may not be fully charged. Because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. This minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. The minimum load generally goes to zero once the circuit has started. Figure 7 shows a plot of minimum load to start and to run as a function of input voltage. In many cases, the discharged output capacitor will present a load to the switcher, which will allow it to start. The plots show the worst-case situation where VIN is ramping very slowly. For lower start-up voltage, the boost diode can be tied to VIN ; however, this restricts the input range to one-half of the absolute maximum rating of the BST pin. At light loads, the inductor current becomes discontinuous and the effective duty cycle can be very high. This reduces the minimum input voltage to approximately 300mV above VOUT. At higher load currents, the inductor current is continuous and the duty cycle is limited by the maximum duty cycle of the LT3688, requiring a higher input voltage to maintain regulation. There is one particular issue to note if sequencing is used. If the BIAS pin is tied to VOUT2, it will be low during the startup of VOUT1. This will prevent the boost circuit from working on VOUT1 until it has risen to 90% of its programmed value, increasing the required startup voltage. Using circuit in Figure 6b for VOUT1 will reduce the startup voltage to its normal value. An alternative is to tie BIAS to VOUT1, if it is greater than 2.8V. Soft-Start and Individual Channel Shutdown The RUN/SS (Run/Soft-Start) pins are used to place the individual switching regulators in shutdown mode. They also provide a soft-start function. To shut down either
INPUT VOLTAGE (V) 8 7.5 TO START 7 6.5 6 5.5 5 4.5 4 1 10 LOAD (mA)
3688 F07a
VOUT = 5V
TO RUN
100
1000
7.0 6.5 6.0 INPUT VOLTAGE (V) 5.5 5.0 4.5 4.0
VOUT = 3.3V
TO START
TO RUN 3.5 3.0 1 10 LOAD (mA)
3688 F07b
100
1000
Figure 7. The Minimum Input Voltage Depends on Output Voltage, Load Current and Boost Circuit
regulator, pull the RUN/SS pin to ground with an opendrain or collector. Note that if CONFIG is tied high or low (not open), shutting down Channel 1 will also shut down Channel 2 because of the sequencing function (See the Configuration and Sequencing section for more details). 2.5A current sources pull up on each pin. If the RUN/SS pin reaches ~0.2V, the channel will begin to switch If a capacitor is tied from the RUN/SS pin to ground, then the internal pull-up current will generate a voltage ramp on this pin. This voltage clamps the VC pin, limiting the peak switch current and therefore input current during start up. A good value for the soft-start capacitor is COUT/10,000, where COUT is the value of the output capacitor. The RUN/SS pins can be left floating if the Soft-Start feature is not used. They can also be tied together with a single capacitor providing soft-start. The internal current sources
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LT3688 APPLICATIONS INFORMATION
will charge these pins to ~2V. The RUN/SS pins provide a soft-start function that limits peak input current to the circuit during start-up. This helps to avoid drawing more current than the input source can supply or glitching the input supply when the LT3688 is enabled. The RUN/SS pins do not provide an accurate delay to start or an accurately controlled ramp at the output voltage, both of which depend on the output capacitance and the load current. Synchronization Synchronizing the LT3688 oscillator to an external frequency can be done by connecting a square wave (with positive and negative pulse width > 150ns) to the SYNC pin. The square wave amplitude should have valleys that are below 0.4V and peaks that are above 1.3V (up to 6V). The LT3688 may be synchronized over a 350kHz to 2.5MHz range. The RT resistor should be chosen to set the LT3688 switching frequency 20% below the lowest synchronization input. For example, if the synchronization signal will be 350kHz and higher, RT should be chosen for 280kHz. To assure reliable and safe operation, the LT3688 will only synchronize when the output voltage is above 90% of its regulated voltage. It is therefore necessary to choose a large enough inductor value to supply the required output current at the frequency set by the RT resistor (see the Inductor Selection section). It is also important to note that the slope compensation is set by the RT value. When the sync frequency is much higher than the one set by RT, the slope compensation will be significantly reduced, which may require a larger inductor value to prevent subharmonic oscillation. Shutdown and Undervoltage Lockout Figure 8 shows how to add undervoltage lockout (UVLO) to the LT3688. Typically, UVLO is used in situations where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. UVLO prevents the regulator from operating at source voltages where the problems might occur. An internal comparator will force the part into shutdown below the minimum VIN of 3.5V. This feature can be used to prevent excessive discharge of battery-operated systems. If an adjustable UVLO threshold is required, the EN/UVLO pin can be used. The threshold voltage of the EN/UVLO pin comparator is 1.25V. Current hysteresis is added above the EN threshold. This can be used to set voltage hysteresis of the UVLO using the following: R3 = R4 = VH - VL 3.7A R3 * 1.25V VH - 1.25V - R3 * 0.3A
Example: switching should not start until the input is above 4.40V, and is to stop if the input falls below 4V. VH = 4.40V, VL = 4V R3 = R4 = 4.40V - 4V = 107k 3.7A 107k * 1.25V = 43.2k 4.40V - 1.25V - 107k * 0.3A
LT3688 1.25V R3 EN/UVLO
VIN
VC
C1
R4
0.3A
3.7A
Figure 8. Undervoltage Lockout
Keep the connection from the resistor to the EN/UVLO pin short and make sure the interplane or surface capacitance to switching nodes is minimized. If high resistor values are used, the EN/UVLO pin should be bypassed with a 1nF capacitor to prevent coupling problems from the switch node.
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+
RUN/SS
3688 F08
-
LT3688 APPLICATIONS INFORMATION
Output Voltage Monitoring The LT3688 provides power supply monitoring for microprocessor-based systems. The features include power-on reset (POR) and watchdog timing. A precise internal voltage reference and glitch immune precision POR comparator circuits monitor the LT3688 output voltages. Each channel's output voltage must be above 90% of the programmed value for RST not to be asserted (refer to the Timing Diagram). The LT3688 will assert RST during power-up, power-down and brownout conditions. Once the output voltage rises above the RST threshold, the adjustable reset timer is started and RST is released after the reset timeout period. On power-down, once the output voltage drops below RST threshold, RST is held at a logic low. The reset timer is adjustable using external capacitors. This capability helps hold the microprocessor in a stable shutdown condition. The RST pin has weak pull-up to the BIAS pin. The above discussion is concerned only with the DC value of the monitored supply. Real supplies also have relatively high-frequency variation, from sources such as load transients, noise, and pickup. These variations should not be considered by the monitor in determining whether a supply voltage is valid or not. The variations may cause spurious outputs at RST, particularly if the supply voltage is near its trip threshold. Two techniques are used to combat spurious reset without sacrificing threshold accuracy. First, the timeout period helps prevent high-frequency variation whose frequency is above 1/ tRST from appearing at the RST output. When the voltage at FB goes below the threshold, the RST pin asserts low. When the supply recovers past the threshold, the reset timer starts (assuming it is not disabled), and RST does not go high until it finishes. If the supply becomes invalid any time during the timeout period, the timer resets and starts fresh when the supply next becomes valid. While the reset timeout is useful for preventing toggling of the reset output in most cases, it is not effective at preventing nuisance resets due to short glitches (due to load transients or other effects) on a valid supply. To reduce sensitivity to these short glitches, the comparator has additional anti-glitch circuitry. Any transient at the input of the comparator needs to be of sufficient magnitude and duration (tUV) before it can change the monitor state. The combination of the reset timeout and anti-glitch circuitry prevents spurious changes in output state without sacrificing threshold accuracy. Watchdog Timer The LT3688 includes an adjustable watchdog timer that monitors a P's activity. If a code execution error occurs in a P, the watchdog will detect this error and will set the WDO low. This signal can be used to interrupt a routine or to reset a P . The watchdog circuitry is triggered by negative edges on the WDI pin. The window mode restricts the WDI pin's negative going pulses to appear inside a programmed time window (see the Timing Diagram) to prevent WDO from going low. If more than two pulses are registered in the window's fast period, the WDO is forced to go low. The WDO also goes low if no negative edge is supplied to the WDI pin in the window's slow timer period. During a code execution error, the microprocessor will output WDI pulses that would be either too fast or too slow. This condition will assert WDO and force the microprocessor to reset the program. In window mode, the WDI signal frequency is bounded by an upper and lower limit for normal operation. The WDI input frequency period should be higher than the window mode's fast period and lower than the window mode's slow period to keep WDO high under normal conditions. The window mode's fast and slow times have a fixed ratio of 16 between them. These times can be increased or decreased by adjusting an external capacitor on the CWDT pin. When WDO is asserted, a timer is enabled for a time equivalent to 1/8th of the watchdog window upper boundary. Any WDI pulses that appear while the reset timer is running are ignored. When the timer expires, the WDO is allowed to go high again. Therefore, if no input is applied to the WDI pin, then the watchdog circuitry produces a train of pulses on the WDO pin. The high time of this pulse train is equal to the watchdog window upper boundary, and low time is equal to the 1/8th of the watchdog window upper boundary.
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LT3688 APPLICATIONS INFORMATION
If WDO is low and RST goes low, then WDO will go high. The WDE pin allows the user to turn on and off the watchdog function. Leaving this pin open is okay and will automatically enable the watchdog. It has an internal weak pull-down to ground. The WDI pin has an internal weak pull-up that keeps the WDI pin high. If watchdog is disabled, leaving this pin open is acceptable. Configuration and Sequencing Use the CONFIG pin to adjust the sequencing and the behavior of the power-on reset and watchdog timers. The table below shows all of the configuration options.
Table 5. Configuration Options CONFIG CONDITION
Channel 1 starts before Channel 2 Channel 1 and Channel 2 start simultaneously Watchdog operates only if Reset 1 Expires Watchdog operates only if Reset 1 and Reset 2 Expire RST1 and RST2 high only if Timer 1 Expires RST1 and RST2 use independent timers x x x x x
VOUT1 (10V/DIV) VOUT2 (10V/DIV) RST1 (5V/DIV) RST2 (5V/DIV) WDO (5V/DIV) WDI (10V/DIV) VOUT1 (10V/DIV) VOUT2 (10V/DIV) RST1 (5V/DIV) RST2 (5V/DIV) WDO (5V/DIV) WDI (10V/DIV)
10ms/DIV
3688 F09a
Figure 9a. CONFIG = HIGH
VOUT1 (10V/DIV) VOUT2 (10V/DIV) RST1 (5V/DIV) RST2 (5V/DIV) WDO (5V/DIV)
HIGH LOW OPEN
x x x x
WDI (10V/DIV)
10ms/DIV
3688 F09b
Figure 9b. CONFIG = LOW
With the CONFIG pin tied high, VOUT1 will rise first, as shown in Figure 9a. After VOUT1 reaches VUV, VOUT2 will start increasing. In addition, the reset timer for Channel 1 starts. Once VOUT2 reaches VUV, the reset timer for Channel 2 starts. Once the reset timers for both Channel 1 and Channel 2 have expired, the Watchdog will start operation. With the CONFIG pin tied low, VOUT1 will rise first. After VOUT1 reaches VUV, VOUT2 will start increasing. The reset timer will only start if both VOUT1 and VOUT2 are above VUV, as shown in Figure 9b. Once the reset timer programmed by CPOR1 expires, both RST1 and RST2 can pull high, and the Watchdog will start operation. In this mode, tie CPOR2 to GND. With the CONFIG pin open, VOUT1 and VOUT2 can rise simultaneously, as shown in figure 9c. After VOUT1 reaches VUV the reset timer for Channel 1 starts. Once VOUT2 reaches VUV, the reset timer for Channel 2 starts. Once the reset timer for Channel 1 has expired, the Watchdog will start operation.
10ms/DIV
3688 F09c
Figure 9c. CONFIG = OPEN Figure 9. Startup Waveforms with the Three Configuration Settings
Selecting the Reset Timing Capacitors The reset timeout period is adjustable in order to accommodate a variety of microprocessor applications. The reset timeout period, tRST, is adjusted by connecting a capacitor, CPOR, between the CPOR pin and ground. The value of this capacitor is determined by:
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LT3688 APPLICATIONS INFORMATION
pF CPOR = t RST * 200 ms This equation is accurate for reset timeout periods of 1ms, or greater. To program faster timeout periods, see the Reset Timeout Period vs Capacitance graph in the Typical Characteristics section. Leaving the CPOR pin unconnected will generate a minimum reset timeout of approximately 65s. Maximum reset timeout is limited by the largest available low leakage capacitor. The accuracy of the timeout period will be affected by capacitor leakage (the nominal charging current is 2.5A), capacitor tolerance and temperature coefficient. A low leakage, low tempco, capacitor is recommended. Selecting the Watchdog Timing Capacitor The watchdog timeout period is adjustable and can be optimized for software execution. The watchdog window upper boundary, tWDU is adjusted by connecting a capacitor, CWDT, between the CWDT pin and ground. Given a specified watchdog timeout period, the capacitor is determined by: pF CWDT = t WDU * 50 ms The window lower boundary (tWDL) and the watchdog timeout (tWDTO) have a fixed relationship to tWDU for a given capacitor. The window lower boundary is related to tWDU by the following: 1 t WDL = * t WDU 16 The watchdog timeout is related to tWDU by the following: 1 tWDTO = *tWDU 8 Leaving the CWDT pin unconnected will generate a minimum watchdog window upper boundary of approximately 200s. Maximum window upper boundary is limited by the largest available low leakage capacitor. The timing accuracy of the reset and watchdog signals depends on the initial accuracy and stability of the programing capacitors. Use capacitors with specified accuracy, leakage and voltage and temperature coefficients. For surface mount ceramic capacitors C0G and NP0 types are superior to alternatives such as X5R and X7R. Shorted and Reversed Input Protection If an inductor is chosen to prevent excessive saturation, the LT3688 will tolerate a shorted output. When operating in short-circuit condition, the LT3688 will reduce its frequency until the valley current is at a typical value of 1.2A (see Figure 12). There is another situation to consider in systems where the output will be held high when the input to the LT3688 is absent. This may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode ORed with the LT3688's output. If the VIN pin is allowed to float and the EN/UVLO pin is held high (either by a logic signal or because it is tied to VIN), then the LT3688's internal circuitry will pull its quiescent current through its SW pin. This is fine if the system can tolerate a few mA in this state. If the EN/UVLO pin is grounded, the SW pin current will drop to essentially zero. However, if the VIN pin is grounded while the output is held high, then parasitic diodes inside the LT3688 can pull large currents from the output through the SW pin and the VIN pin. Figure 13 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input.
VSW 10V/DIV
IL 500mA/DIV
5s/DIV
3688 F12
Figure 12. The LT3688 Reduces Its Frequency to Below 70kHz to Protect Against Shorted Output with 36V Input
PCB Layout For proper operation and minimum EMI, care must be taken during printed circuit board layout. Figure 14 shows the recommended component placement with trace, ground plane and via locations. Note that large, switched currents flow in the LT3688's VIN, DA and SW pins, the catch diode (D1) and the input capacitor (C1). The loop formed by
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23
LT3688 APPLICATIONS INFORMATION
D4 VIN VIN BIAS BOOST LTC3688 SW DA EN/UVLO GND FB VOUT
keep thermal resistance low, extend the ground plane as much as possible, and add thermal vias under and near the LT3688 to additional ground planes within the circuit board and on the bottom side. High Temperature Considerations The PCB must provide heat sinking to keep the LT3688 cool. The exposed pad on the bottom of the package must be soldered to a ground plane. This ground should be tied to large copper layers below with thermal vias; these layers will spread the heat dissipated by the LT3688. Placing additional vias can reduce thermal resistance further. With these steps, the thermal resistance from die (or junction) to ambient can be reduced to JA = 40C/W or less. With 100 LFPM airflow, this resistance can fall by another 25%. Further increases in airflow will lead to lower thermal resistance. Because of the large output current capability of the LT3688, it is possible to dissipate enough heat to raise the junction temperature beyond the absolute maximum of 125C (150C for H Grade). When operating at high ambient temperatures, the maximum load current should be derated as the ambient temperature approaches 125C (150C for H Grade). Power dissipation within the LT3688 can be estimated by calculating the total power loss from an efficiency measurement and subtracting the catch diode loss. The die temperature is calculated by multiplying the LT3688 power dissipation by the thermal resistance from junction-to-ambient. Thermal resistance depends on the layout of the circuit board, but values from 30C/W to 60C/W are typical. Die temperature rise was measured on a 4-layer, 5cm * 7.5cm circuit board in still air at a load current of 0.8A (fSW = 800kHz). For a 12V input to 3.3V output the die temperature elevation above ambient was 14C; for 12VIN to 5VOUT the rise was 15C and for 12VIN to 5VOUT and 3.3VOUT the rise was 30C. Other Linear Technology Publications Application Notes 19, 35 and 44 contain more detailed descriptions and design information for buck regulators and other switching regulators. The LT1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. Design Note 318 shows how to generate a bipolar output supply using a buck regulator.
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+
3688 F13
Figure 13. Diode D4 Prevents a Shorted Input from Discharging a Backup Battery Tied to the Output; It Also Protects the Circuit from a Reversed Input. The LT3688 Runs Only When the Input Is Present
3688 F14
Figure 14. Top Layer PCB Layout in the LT3688 Demonstration Board
these components should be as small as possible. These components, along with the inductor and output capacitor, should be placed on the same side of the circuit board. Place a local, unbroken ground plane below these components. The SW and BST nodes should be as small as possible. Finally, keep the FB node small so that the ground traces will shield them from the SW and BST nodes. The exposed pad on the bottom of the package must be soldered to ground so that the pad acts as a heat sink. To
24
LT3688 TYPICAL APPLICATIONS
VIN 6V TO 36V C1 4.7F EN/UVLO BST1 SW1 C6 10pF C4 22F R1 523k C8 1nF D1 DA1 FB1 CONFIG RUN/SS1 WDE I/O I/O RESET P WDI WDO RST1 RST2 RUN/SS2 CWDT CPOR1 CPOR2 RT SYNC LT3688 DA2 FB2 VIN BIAS BST2 SW2 L2 12H R3 316k R4 100k C7 10pF
VOUT1 5V 800mA
ON OFF L1 18H
C2 0.22F
C3 0.22F D2
VOUT2 3.3V 800mA
R2 100k
C9 1nF
C5 22F
C10 4.7nF R5 110k C11 4.7nF C12 1nF
3688 TA02
GND
C1-C5: X5R OR X7R D1, D2: DIODES INC. B140
fSW = 500kHz
5V and 3.3V Regulator with Power-On Reset and Watchdog Timers
VIN 8V TO 36V
C1 4.7F
R6 475k R7 100k L1 10H
VIN EN/UVLO C2 0.22F D1 DA1 FB1 BST1 SW1
CONFIG BIAS BST2 SW2 C3 0.22F D2 DA2 FB2 RUN/SS2 CWDT CPOR1 CPOR2 RT SYNC L2 12H R3 316k R4 100k C7 10pF
VOUT 1.8V 800mA
C6 10pF C4 47F
R1 187k R2 150k C8 1nF
LT3688
VOUT2 3.3V 800mA
C9 1nF
C5 22F
RUN/SS1 WDE I/O I/O RESET P WDI WDO RST1 RST2
C10 4.7nF R5 110k fSW = 500kHz C11 4.7nF C12 1nF
3688 TA02
GND
C1-C5: X5R OR X7R D1, D2: DIODES INC. B140
3.3V and 1.8V Regulator with Power-On Reset and Watchdog Timers and Input Under Voltage Lockout
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25
LT3688 TYPICAL APPLICATIONS
VIN 6V TO 36V C1 4.7F EN/UVLO BST1 SW1 C6 10F C4 10F R1 523k R2 100k C8 1nF D1 DA1 FB1 CONFIG RUN/SS1 WDE I/O I/O RESET P WDI WDO RST1 RST2 RUN/SS2 CWDT CPOR1 CPOR2 RT SYNC LT3688 DA2 FB2 VIN BIAS BST2 SW2 L2 8.2H R3 316k R4 100k C7 10pF
ON OFF VOUT1 5V 800mA L1 8.2H C2 0.1F
C3 0.1F D2
VOUT2 3.3V 800mA
C9 1nF
C5 22F
C10 4.7nF R5 20k C11 4.7nF C12 1nF
3688 TA04
GND
C1-C5: X5R OR X7R D1, D2: DIODES INC. B140
fSW = 2MHz: 8V < VIN < 16V, TJ < 85C
2MHz Switching Frequency, 5V and 3.3V Regulator with Power-On Reset and Watchdog Timers
VIN 4V TO 36V
C1 4.7F EN/UVLO BST1 SW1
VIN BIAS BST2 SW2 LT3688 DA1 FB1 CONFIG RUN/SS1 RUN/SS2 CWDT CPOR1 CPOR2 RT SYNC WDE WDI WDO RST1 RST2 DA2 FB2 L2 15H R3 316k R4 100k C7 10pF
VOUT1 1.2V 800mA
ON OFF L1 8.2H C6 10pF C4 100F D1 R1 90.9k R2 182k C8 1nF
C2 0.22F
C3 0.22F D2
VOUT2 3.3V 800mA
C9 1nF
C5 22F
WATCHDOG DEFEAT P I/O
C10 4.7nF R5 143k C11 4.7nF C12 1nF
3688 TA05
RESET
GND
C1-C5: X5R OR X7R D1, D2: DIODES INC. B140
fSW = 400kHz: VIN < 25V
3.3V and 1.2V Regulator with Power-On Reset Timer and Defeatable Watchdog, Timing Error Resets Microprocessor
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26
LT3688 PACKAGE DESCRIPTION
FE Package 24-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1771 Rev O)
Variation AA
3.25 (.128) 7.70 - 7.90* (.303 - .311) 3.25 (.128) 24 23 22 21 20 19 18 17 16 15 14 13
6.60 0.10 4.50 0.10
SEE NOTE 4
2.74 (.108) 0.45 0.05 1.05 0.10 0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
6.40 2.74 (.252) (.108) BSC
1 2 3 4 5 6 7 8 9 10 11 12 1.20 (.047) MAX
0 -8
4.30 - 4.50* (.169 - .177)
0.25 REF
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE24 (AA) TSSOP 0208 REV O
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
UF Package 24-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1697)
BOTTOM VIEW--EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER 23 24 0.40 0.10 1 2 4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES) 2.45 0.10 (4-SIDES)
4.00 0.10 (4 SIDES) 0.70 0.05 PIN 1 TOP MARK (NOTE 6)
0.75 0.05
R = 0.115 TYP
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
(UF24) QFN 0105
0.25 0.05 0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3688 TYPICAL APPLICATION
VIN 6V TO 36V C1 4.7F EN/UVLO BST1 SW1 C6 10pF C4 22F R1 523k C8 1nF D1 DA1 FB1 CONFIG RUN/SS1 WDE I/O I/O RESET C1-C5: X5R OR X7R D1, D2: DFLS140 P WDI WDO RST1 RST2 RUN/SS2 CWDT CPOR1 CPOR2 RT SYNC LT3688 DA2 FB2 VIN BIAS BST2 SW2 L2 12H R3 340k R4 100k C7 10pF
VOUT1 5V 800mA
ON OFF L1 18H
C2 0.22F
C3 0.22F D2
VOUT2 3.3V 800mA
R2 100k
C9 1nF
C5 22F
C10 4.7nF R5 49.9k C11 4.7nF C12 1nF
3688 TA06
GND
fSW = 1MHz: 7V < VIN < 21V
1MHz 5V and 3.3V Regulator with Power-On Reset and Watchdog Timers
RELATED PARTS
PART NUMBER LT3640 LT3689/LT3689-5 DESCRIPTION 35V, 55V MAX, Dual (1.3A, 1.1A), 2.5MHz High Efficiency StepDown DC/DC Converter with POR Reset and Watchdog Timer 36V, 60V Transient Protection, 800mA, 2.2MHz High Efficiency MicroPower Step-Down DC/DC Converter with POR Reset and Watchdog Timer 37V, 55Vmax, 1.2A, 2.5MHz High Efficiency Step-Down DC/DC Converter 36V, 60Vmax, 1A, 2.2MHz High Efficiency Micropower StepDown DC/DC Converter 38V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down DC/DC Converter with only 2.8uA of Quiescent Current 55V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down DC/DC Converter with only 2.8uA of Quiescent Current 40V, 350mA (IOUT), 2MHz, High Efficiency Step-Down DC/DC Converter with only 2.5uA of Quiescent Current 60V, 350mA (IOUT), 2MHz, High Efficiency Step-Down DC/DC Converter with only 2.5uA of Quiescent Current COMMENTS VIN Min = 4V, VIN Max = 35V, Transient to 55V, VOUT(MIN) = 0.6V, IQ = <290A, ISD = <1A, 4mm x 5mm QFN-28 TSSOP-28E Package VIN Min = 3.6V, VIN Max = 36V, Transient to 60V, VOUT(MIN) = 0.8V, IQ = 75A, ISD = <1A, 3mm x 3mm QFN-16 Package VIN Min = 3.6V, VIN Max = 37V, Transient to 55V, VOUT(MIN) = 1.21V, IQ = 1.1mA, ISD = <1A, 3mm x 3mm DFN-10 Package VIN Min = 3.6V, VIN Max = 36V, VOUT(MIN) = 0.8V, IQ = 75A, ISD = <1A, 3mm x 3mm DFN-12 Package VIN Min = 4.2V, VIN Max = 38V, VOUT(MIN) = 1.2V, IQ = 2.8A, ISD = <1A, 3mm x 3mm DFN-10, MSOP-10E Package VIN Min = 4.2V, VIN Max = 55V, VOUT(MIN) = 1.2V, IQ = 2.8A, ISD = <1A, 3mm x 3mm DFN-10, MSOP-10E Package VIN Min = 4.2V, VIN Max = 40V, VOUT(MIN) = 1.2V, IQ = 2.5A, ISD = <1A, 2mm x 3mm DFN-10, MSOP-10E Package VIN Min = 4.2V, VIN Max = 60V, VOUT(MIN) = 1.2V, IQ = 2.5A, ISD = <1A, 3mm x 3mm DFN-10, MSOP-16E Package
LT3686 LT3682 LT3971 LT3991 LT3970 LT3990
3688f
28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0111 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORA TION 2011

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